The increasing operating speed and computing power of electronic systems has given a rise to the need for memory devices having rapid access times and large capacities. In order to ensure that computing cycles are not wasted by a system, large amounts of data must be provided by a semiconductor memory device at as high a rate as possible.
In a typical read operation, a number of memory cells are selected by the application of an address. The data stored within the memory cells are then accessed according to one or more timing signals. For example, in the case of an asynchronous dynamic random access memory (DRAM), a row address is applied in combination with a row address strobe (RAS) timing signal to select a row of memory cells. A column address is then applied in combination with a column address strobe (CAS) timing signal to access selected cells within the row. In the case of a synchronous DRAM (SDRAM), memory cells are selected according to a system clock.
As semiconductor memory devices increase in capacity, they also typically increase in physical size. Larger physical sizes can impact the overall speed of a device, as data and timing signals must propagate across larger distances, adding to the response time of the device. The placement of the conductive lines (the routing) that carry timing and data signals can thus play an important role in the speed of a memory device.
The millions of memory cells within a high-capacity memory device are typically arranged into a number of arrays that are further divided into a number of array banks. Data is output from each array bank by input/output (I/O) lines. A problem with high-capacity memory devices is that all of the I/O lines must be routed to the same I/O circuit. The I/O circuit includes the input buffers, output buffers, and latches necessary to store incoming data in a write operation, or drive outgoing data in a read operation. In the event the I/O circuits are located in a central portion of the semiconductor memory device, a routing "bottleneck" can occur in the central portion of the device. The bottleneck results in large numbers of I/O lines overlapping one another and limiting the available space in the central portion of the device.
One example of a memory device having a routing bottleneck in a central portion of the device is set forth in FIG. 1. FIG. 1 is a top plan view of a SDRAM, illustrating the placement of memory cell banks and various other circuit blocks. The SDRAM is designated by the general reference character 100, and is shown to include four array banks 102a-102d. In the particular example of FIG. 1, the SDRAM has a storage capacity of 256 megabits (Mb); thus each array bank (102a-102d) includes 64 Mb. Each array bank (102a-102d) is further divided into a first and second sub-banks. The first sub-banks are shown as 104a-104d and the second sub-banks are shown as 106a-106d. The memory cells within each sub-bank are accessed by activating associated row address circuitry 108 and column select circuitry 110.
Data within the SDRAM 100 are accessed by way of a first I/O circuit 112, situated between array banks 102a and 102c, and a second I/O circuit 114, situated between array banks 102b and 102d. The I/O circuits (112 and 114) possess the structures necessary to input data for write operations, and to output data in read operations, including I/O pads. When the SDRAM 100 is active in a read or write cycle, the memory cells within one of the array banks (102a-102d) are accessed. In order to make this possible, each array bank (102a-102d) has a data I/O bus that couples data from the array bank to the I/O circuits (112 and 114). Because there are two I/O circuits (112 and 114), each data I/O bus is further divided into two sub-bank buses. One sub-bank bus couples the data from a first sub-bank (104a for example) to the first I/O circuit 112, while the other sub-bank bus couples the data from a second sub-bank (106a for example) to the second I/O circuit 114.
In the particular example of FIG. 1, the general path of only selected I/O lines is illustrated to not unduly clutter the view of the figure. In particular, the first I/O lines (116a, 116b, 116c and 116d) and last I/O lines (118a, 118b, 118c and 1186d) of the sub-bank buses for array banks 102a and 102b are illustrated. Thus, first I/O line 116a and last I/O line 118a are used to represent a first sub-bank bus 120a that connects first sub-bank 104a with the first I/O circuit 112. A second sub-bank bus 120b connects the second sub-bank 106a to the second I/O circuit 114, and is defined by first I/O line 116b and last I/O line 118b. In the same general fashion, sub-bank bus 120c, defined by first I/O line 116c and last I/O line 118c, connects first sub-bank 104b to first I/O circuit 112, and sub-bank bus 120d, defined by first I/O line 116d and last I/O line 118d, connects second sub-bank 106b to the second I/O circuit 114. It is understood that sub-banks 104c, 106c, 104d and 106d are connected to the first and second I/O circuits (112 and 114) in mirror image fashion.
It is noted that the SDRAM 100 further includes a timing circuit 122 located in the central portion of the device. The timing circuit 122 receives timing signals, such as the system clock signal, and in response thereto, activates circuits within the SDRAM that are necessary to access data within the memory cells. The timing path of a memory cell access operation is shown in FIG. 1 by dashed line 124. In response to a clock signal applied to the timing circuit 122, a signal is activated which runs to the sub-bank 106c, and places data on an I/O line. The I/O line is coupled to an I/O bus line, which connects the sub-bank 106c to the second I/O circuit 114. The central location of the timing circuit 122 allows for shorter timing path distances with respect to all of the array banks. Also set forth in FIG. 1, are the word lines 126 that are activated in order to provide the access operation illustrated by line 124.
Referring now to FIGS. 2A and 2B, a portion of FIG. 1 is set forth in a top plan view to provide one representation of the sub-bank bus lines. FIG. 2A provides a representation of sub-bank buses 120a and 120b. It is understood that each of the bus lines set forth in FIG. 2A represents four actual bus lines, giving a total of 32 bus lines in each sub-bank bus. Sub-bank buses 120c and 120d are omitted in FIG. 2A. FIG. 2B sets forth the same view as FIG. 2A, but omits sub-bank buses 120a and 120b, and includes sub-bank buses 120c and 120d. A comparison between FIGS. 2A and 2B illustrates that sub-bank buses 120b and 120c must both travel over the same location, and so overlap one another in the central portion of the SDRAM. This results in an undesirable routing bottleneck in the center of the device.
Referring now to FIG. 3, a top plan view of an alternate SDRAM architecture is set forth. The SDRAM is designated by the general reference character 300, and is shown to include many of the same general elements as FIG. 1. To this extent, like elements will be referred to by the same reference characters, but with the first number being a "3" instead of a "1." Accordingly, the SDRAM 300 of FIG. 3 includes four array banks (302a-302d), each of which includes a first sub-bank (304a-304d) and a second sub-bank (306a-306d). Unlike the SDRAM 100 of FIG. 1, the array banks (306a-306d) extend in the horizontal direction across the entire SDRAM 300. Similarly, the first and second sub-banks (304a-304d and 306a-306d) extend roughly halfway across the SDRAM in the horizontal direction, as opposed to one-fourth the distance as is the case in FIG. 1. The SDRAM 300 of FIG. 3 includes row address circuitry 308, column select circuitry 310, and first and second I/O circuits (312 and 314), all situated in the same general positions as the SDRAM 100 of FIG. 1.
The SDRAM 300 of FIG. 3 includes first I/O lines 316a-316d and second I/O lines 318a-318d that define sub-bank buses (320a-320d). Unlike the sub-bank buses 120a-120d of FIG. 1 which couple an entire sub-bank to an I/O circuit (112 and 114), the sub-bank buses in FIG. 3 each couple half of a sub-bank to half of an I/O circuit. For example, sub-bank bus 320a couples half of sub-banks 304a and 304b to half of I/O circuit 312. Sub-bank bus 320b couples the remaining halves of sub-banks 304a and 304b to the remaining half of I/O circuit 312. In a similar fashion, sub-bank bus 320c connects half of sub-banks 306a and 306b to half of the second I/O circuit 314, while sub-bank bus 320d connects the other halves of sub-banks 306a and 306b to the other half of the second I/O circuit 314.
Like the SDRAM 100 of FIG. 1, the SDRAM 300 includes a centrally located timing circuit 322, and sets forth a timing path 324 and the word lines 326 that are activated in the access operation of the timing path 324. Unlike the SDRAM 100 in FIG. 1, the sub-bank buses (320a-320d) of the SDRAM 300 of FIG. 3 do not overlap, and leave the central portion of the SDRAM 300 without a routing bottleneck. A drawback to the SDRAM 300 of FIG. 3 is that the overall length of the word lines 326 activated in a given cycle is about twice that of the of the SDRAM 100 of FIG. 1. The additional current required to drive the longer word lines results in the architecture of FIG. 3 consuming more power when a row is accessed than the architecture of FIG. 1.
It would be desirable to arrive at an architecture for a high-speed large capacity memory device that does not present a routing bottleneck toward the center of the device. At the same time, the memory device should not consume too much power.